Input One is intended for a color signal. The Input Module will clamp the signal and strip sync. Timing signals extracted from the Input One signal will be H drive, V drive, blanking, composite sync, subcarrier and burst flag. These signals will be connected to the Sync Generator for gen lock. There will be a manual adjustment for the phase of the subcarrier. The video portion of the Input One signal will be amplified and distributed to the Input One terminal of the analog matrix described later. There will be a manual adjustment for the chrominance of the distributed signal. The video portion of the Input One signal and all the other external video signals will be distributed through the Design Device as non-composite 0 to + 2 Volts.
Hardwired to Input One will be a Chroma Decoder system nearly identical to ones used on "solid state" television receivers. The RGB outputs of the decoder will be analyzed by comparators with manually adjusted thresholds, and the consequent logic pulse will be distributed into the Design Device matrix.
Input Two is for a black and white camera which is used to rescan a RuttEtra Display. The camera will receive its sync from the Design Device sync generator. Input Three is for any vertical lock vtr. This signal is processed through an analog comparator and is then loaded into a one bit time base corrector. The time base of input Three is matched to Input One within a window of one line and will have horizontal resolution of 256 points. Input Four accepts an external video camera, either black and white or encoded color, which is synched from the Design Device Sync Generator.
The Input Module will drive a video Sync Generator which will synthesize all timing signals not derived from Input One. In the case of a black and white signal, the Sync Generator will provide a free running 3.58 MHz subcarrier and a horizontal drive triggered color burst flag which can be used to synthesize color. In the case of an EIAJ heterodyned color signal, the subcarrier will be derived from the incoming signal. In these cases, the output of the Design Device will not be directly broadcast compatible, but it may be made so by subsequent time base correction. The Sync Generator will also provide a 4.09084 MHz clock pulse ( 260 x H) phase locked to the subcarrier and 15,750 and 60 Hz sawteeth triggered by the horizontal and vertical drives.
The signal processing modules of the Design Device will consist of individually addressable voltage controlled and digital devices with compatible inputs and outputs. Control voltages will have a +5 volt range.
The primary oscillator of the Design Device will be an 256 x 8 bit random access memory (RAM) with an 8 bit digital to analog converter (DAC) as an output buffer. The contents of the memory
